?002 fairchild semiconductor corporation RFG75N05E rev. b RFG75N05E 75a, 50v, 0.008 ohm, n-channel power mosfet these are n-channel enhancement mode silicon gate power ?ld effect transistors. they are advanced power mosfets designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta09821. features 75a, 50v ? ds(on) = 0.008 ? electrostatic discharge rated uis rating curve (single pulse) 175 o c operating temperature temperature compensated pspice model provided symbol packaging jedec style to-247 ordering information part number package brand RFG75N05E to-247 RFG75N05E note: when ordering, include the entire part number. g d s drain (bottom side metal) source drain gate january 2002 data sheet
?002 fairchild semiconductor corporation RFG75N05E rev. b absolute maximum ratings t c = 25 o c, unless otherwise speci?d RFG75N05E units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v dss 50 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 50 v continuous drain current (current limited by package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 75 a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 200 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d 240 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 w/ o c electrostatic discharge rating, mil-std-883, category b(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e sd 2kv single pulse avalanche rating (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to uis soa curves operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss v gs = 0v, i d = 250 a (figure 9) 50 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 8) 2.0 - 4.0 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 1 a v ds = 0.8 x rated bv dss , v gs = 0v, t c = 150 o c- -25 a gate to source leakage i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) v gs = 10v, i d = 75a (figure 7) - - 0.008 ? turn on time t (on) v dd = 25v, i d 37.5a, r l = 0.67 ? , r g = 1.67 ?, v gs = 10v, (figure 11) - - 125 ns turn on delay time t d(on) -17- ns rise time t r -75- ns turn off delay time t d(off) -70- ns fall time t f -17- ns turn off time t (off) - - 125 ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 0, 20v v dd = 40v, i d = 75a, r l = 0.53 ? i g(ref) = 3.44ma (figure 11) - - 400 nc gate charge at 10v q g(10) v gs = 0, 10v - - 220 nc threshold gate charge q g(th) v gs = 0, 2v - - 15 nc junction to case r jc - - 0.625 o c/w junction to ambient r ja --80 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 75a - - 1.5 v diode reverse recovery time t rr i sd = 75a, di sd /dt = 100a/ s - - 125 ns notes: 2. pulse test: pulse width 300 s, duty cycle 2%. 3. repetitive pulse: pulse width is limited by maximum junction temperature. 4. refer to fairchild application notes an9321 and an9322. see figure 4. RFG75N05E
?002 fairchild semiconductor corporation RFG75N05E rev. b typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. forward bias safe operating area figure 4. unclamped inductive switching soa (single pulse uis soa) figure 5. saturation characteristics figure 6. transfer characteristics t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 25 50 75 100 125 150 t c , case temperature ( o c) i d , drain current (a) 80 70 60 50 40 30 20 10 0 175 v ds , drain to source voltage (v) 10 1 100 1 i d , drain current (a) 10 2 10 operation in this area may be limited by r ds(on) dc i d max continuous t c = 25 o c t j = max rated single pulse 100 1000 10 i as , avalanche current (a) t av , time in avalanche (ms) 110 0.01 0.10 t av = (l)(i as )/(1.3 rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3 rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c idm v ds, drain to source voltage (v) 1.5 3.0 4.5 6.0 0 7.5 200 160 120 0 80 i d , drain current (a) t c = 25 o c 40 v gs = 10v v gs = 5.0v v gs = 6.0v v gs = 4.0v v gs = 7.0v pulse duration = 80 s duty cycle = 0.5% max 04610 2 0 80 120 200 i ds(on) , drain to source current (a) v gs , gate to source voltage (v) 160 40 -55 o c 8 175 o c v dd > i d x r ds(on) pulse duration = 80 s duty cycle = 0.5% max 25 o c RFG75N05E
?002 fairchild semiconductor corporation RFG75N05E rev. b figure 7. normalized drain to source on resistance vs junction temperature figure 8. normalized gate threshold voltage vs junction temperature figure 9. normalized drain to source breakdown voltage vs junction temperature figure 10. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260. figure 11. normalized switching waveforms for constant gate current typical performance curves unless otherwise speci?d (continued) 3.0 2.0 1.0 -50 t j , junction temperature ( o c) normalized drain to source 2.5 1.5 0 100 on resistance 0 50 150 200 i d = 75a, v gs = 10v 0.5 pulse duration = 80 s duty cycle = 0.5% max 2.0 1.2 0.4 -50 t j , junction temperature ( o c) normalized gate 1.6 0.8 0 0 200 threshold voltage 50 100 150 i d = 250 a v gs = v ds 2.0 1.0 0.5 50 -50 t j , junction temperature ( o c) normalized drain to source 1.5 0 100 200 breakdown voltage 0 150 i d = 250 a 0 101520 25 c, capacitance (pf) v ds, drain to source voltage (v) 6000 4000 2000 0 5 c rss c iss c oss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd gate source voltage 50 40 30 10 0 20 i g ref () i g act () ------------------------ - t, time ( s) 80 i g ref () i g act () ------------------------ - 10 8 6 2 0 v ds , drain to source voltage (v) v gs , gate to source voltage (v) v dd = 0.75 bv dss v dd = 0.50 bv dss v dd = 0.25 bv dss 20 v dd = bv dss v dd = bv dss 4 drain source voltage r l = 0.667 ? i g(ref) = 3.44ma v gs = 10v RFG75N05E
?002 fairchild semiconductor corporation RFG75N05E rev. b test circuits and waveforms figure 12. unclamped energy test circuit figure 13. unclamped energy waveforms figure 14. switching time test circuit figure 15. resistive switching waveforms figure 16. gate charge test circuit figure 17. gate charge waveform t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 RFG75N05E
?002 fairchild semiconductor corporation RFG75N05E rev. b pspice electrical model .subckt rfg75n05 2 1 3 ; rev 10/30/90 *nominal temperature = 25 o c ca 12 8 8.98e-9 cb 15 14 8.81e-9 cin 6 8 4.48e-9 dplcap 10 5 dplcapmod dbody 7 5 dbodymod dbreak 5 11 dbreakmod eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 ebreak 11 7 17 18 58.4 evtemp 20 6 18 8 1 it 8 17 1 ldrain 2 5 e-10 lgate 1 9 5e-9 lsource 3 7 3e-9 mos 16 6 8 8 modmod rbreak 17 18 rbreakmod 1 rdrain 5 16 rsourcemod 3.07e-3 rgate 9 20 1.2 rin 6 8 1e9 rsource 8 7 rsourcemod 2.e-3 rvtemp 18 19 rvtonegmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2amod vbat 8 19 dc 1 .model s1amod vswitch (ron=1e-5 roff=0.1 von=-2.48 voff=-0.48) .model s1bmod vswitch (ron=1e-5 roff=0.1 von=0.48 voff=-2.48) .model s2amod vswitch (ron=1e=5 roff=0.1 von=-2.25 voff=2.75) .model s2abmod vswitch (ron=1e-5 roff=0.1 von =2.75 voff=-2.25) .model dbodymod d (is=2.23e-12 rs=249e-3 trs1=2.5e-3 cjo=7.55e-9 tt=4e-8) .model dbreakmod d (rs=8e-2 trs1=2.5e-3) .model dplcapmod d (is=1e-30 n=10 cjo=2.14e-9) .model rbreakmod res (tc1=9.5e-4 tc2=-1.17e-6) .model rsourcemod res (tc1=5.2e-3 tc2=1.37e-5) .model rvtonegmod res (tc1=-3.78e-3 tc2=-7.51e-7) .model modmod nmos (vto=3.48 n=10 is=1e-30 kp=78.5 tox=1 l=1u w1u) .ends 1 gate rgate evto 18 22 9 + 12 13 8 14 13 13 15 s1a s1b s2a s2b ca cb egs eds cin dbreak ebreak dbody drain rsource source rbreak rvtemp vbat it esg dplcap 6 6 8 10 5 16 11 17 18 8 14 5 8 6 8 7 3 17 18 19 2 + + + + + mos lsource ldrain lgate 20 8 rdrain rin RFG75N05E
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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